B.Tech VLSI Projects titles

Latest VLSI Projects titles


  1. An Efficient Nikhilam Vedic Multiplier with Carry Save Adder for DSP Applications
  2. Implementation of efficient code converters using reversible logic gates using Verilog HDL.
  3. High-Performance High-Valency Lander Fischer Adders using Verilog HDL..
  4. An efficient 32- Bit Ripple Carry Adder Based on Reversible logic gates.
  5. High speed Booth multiplier for both signed and unsigned numbers using Verilog HDL .
  6. VLSI Implementation of Industrial chemical tank level indicator using Verilog HDL.
  7. Implementation and Analysis of Power, Area and Delay of CSA, CLA and RCA Adder Blocks. 
  8. A high speed application based item dispense (Vending) machine controller using FSM.
  9. Advanced high securgrity data transmission using S-box in AES algorithm using Verilog HDL.
  10. Design of High Performance 16-bit MAC Unit for DSP and DIP applications using Verilog HDL.
  11. Design and implementation of Spanning tree adder using Verilog HDL.
  12. High security data transmission Algorithm for DES Cryptanalysis using Verilog HDL.
  13. Low-Power and Area-Efficient Carry Select Adder for ALU module in Electronics devices based on RCA using Verilog HDL.
  14. Design And Implementation of Random Pattern Generator For Design Under Test Using Verilog HDL .
  15. Implementation of automatic high speed Washing Machine using Verilog HDL.
  16. Design and implementation of parallel prefix sparse kogee adder using verilog HDL.
  17. Design and implementation of advanced high speed Wallace tree multiplier for DSP and DIP applications using Verilog HDL.
  18. Implementations of Innovative automated teller machine (ATM) controller for financial transactions of having both deposit and withdraw using Verilog HDL.
  19. Design and implementation of kogge stone adder using verilog HDL.
  20. Design and implementation of breunt-kung adder using Verilog HDL.
  21. An Innovative Traffic light control system at junction points for avoiding accidents using Verilog HDL.
  22. Implementation of First in First out (FIFO) design for avoiding data losses in transmission using Verilog HDL.
  23. High speed comparator implementation for Core i7-3770K.
  24. Design and simulation of UART serial communication module based on VHDL.
  25. VLSI Implementation of ALU based on Reversible logic.
  26. Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA.
  27. Design of S2P and P2S Architectures. 
  28. VLSI implementation of Memory Core design using VHDL.
  29. Implementation of 32-bit Cyclic redundancy checker (CRC).